A memory cell, e.g., a static random-access memory (SRAM) cell, may develop a disturb failure during an operation of the memory cell. A SRAM memory cell typically has a word line and two bit lines. In an example, the wordline of a SRAM memory cell is turned ON and the two bit lines are precharged, and the memory cell is said to be disturbed (i.e., has undergone a disturb failure) if the content of the memory cell is flipped (corrupted) to an opposite state, without an explicit write command to flip the state. The unintentional flipping of the content of the memory cell leads to a corruption of the data stored in the memory cell, thereby leading to the disturb failure of the memory cell.
Disturb failure in a memory cell may occur, for example, due to mismatch in the transistors within the memory cell, noise in the transistors, imbalance among the transistors, etc. As semiconductor memory devices continue having lower geometry with advancement of technology, the memory devices are becoming more prone to such disturb failures.
For example, in a SRAM memory, many memory cells are usually connected to a single word line. During a read operation, as many memory cells are connected to the single word line, all the memory cells along the accessed word line are enabled simultaneously (i.e., the memory cells are coupled to their respective bit lines). However, not all the bit lines from the memory cells are connected to sense amplifiers. Only bits lines of those memory cells, which are to be read, are connected to the sense amplifiers via local and/or global multiplexers. In other words, not all the memory cells along the accessed word line are read. Despite not being read, when the memory cells are imbalanced or mismatched, the act of connecting them to bit lines that are pre-charged to the supply voltage (e.g., VDD) can result in cell upsets or data corruption. One reason for the data corruption may be a low threshold voltage VT on a driver transistor of the side of the memory cell where a data “1” is stored. Another reason for the data corruption may be that the load transistors are weak or mismatched. Such data corruption leads to a disturb failure in the memory cell.
Some memory cells may be more prone to a disturb failure than other memory cells. For example, assume a SRAM memory having at least a first memory cell and a second memory cell, where a first plurality of transistors included in the first memory cell have some mismatches (or where a transistor of the first memory cell is relatively weak). Accordingly, the first memory cell may be more prone to disturb failure while in use (e.g., compared to the second memory cell). However, during a conventional testing of the memory (e.g., in which the memory cells of the memory are repeatedly read and/or written to), it may not be easily possible to identify that the first memory cell is more prone to disturb failure, as the first memory cell may not fail during testing (but may fail during actual use).